1. Field of the Invention
This invention relates to a time-division multiplexing apparatus for time-division multiplexing each bit of channels of m-bit byte serial digital input signals to m-bit byte parallel digital signals;
2. Description of the Related Art
In general, an apparatus for time-division multiplexing n channels of m-bit byte serial digital signals; is constructed as shown in FIG. 1. In this multiplexing apparatus, each bit of signals Il-In (n is a natural number more than m) input in synchronous to a transmission clock frequency of fO is time-division multiplexed to 8-bit byte parallel digital signals (i.e., m=8). Specifically, in the apparatus, the signals (8-bit byte serial digital signals input in synchronous to clock pulses CLKl of a frequency f0) Il-In are supplied to 8-stage shift registers SRl-SRn, respectively. The shift registers SRl-SRn each operate in synchronous to clock pulses CLKl. The 8-bit outputs of the registers SRl-SRn are supplied to 8-bit D latches L3l-L3n, respectively Clock pulses, whose frequency is 1/8 of that of the clock pulses CLKl, obtained by dividing the clock pulses CLKl by means of a 1/8 divider 31, are used as latch pulses LP for determining respective latch time points of the D latches L31-L3n.
In FIG. 1, the outputs of the bits of the D latches L31-L3n are denoted by L010-L017, L021-L027, . . . , LOn0-LOn7, in the order from the top, and are supplied to (n : 1) selectors SEL1-SEL8, respectively. A selector control section 32 generates gate pulses GPl-GPn for determining respective selection channels of the selectors SEL1-SEL8. Specifically, the control section 32 generates n-bit gate pulses GPl-GPn of a width 8/(n.times.fO) corresponding to each channel in synchronous to clock pulses CLK2 having a frequency of n.times.fO/8, and supplies them to the selectors SELl-SELn. The selectors in turn perform multiplexing by using the gate pulses GPl-GPn.
FIG. 2 shows an example of multiplexing performed in the above-described apparatus, i.e. shows a procedure for obtaining an output 01 from the selector SELl. In this figure, reference codes S10, S20, . . . , SnO denote the outputs of the shift registers SR1, SR2, . . . , SRn supplied with the n-channel signals I1, I2, . . . , In, respectively, reference symbol LP a latch pulse (for latching each input signal at rising), reference codes LO10, L020, . . . , LOn0 the 0th-bit outputs of D latch L31, L32, . . . , L3n, respectively, reference codes GPl, GP2, . . . , GPn gate pulses for selecting 1, 2, . . . , n channels, respectively, and reference code 01 the output of the selector SELl.
In the above-described apparatus, the relationship between the 0th-bit output of each of the D latches L31-L3n and the rising and falling of the gate pulses GPl-GPn for the selectors SEL1-SEL8 is shown in FIG. 3. Similarly, FIG. 4 shows the relationship between the 7th-bit output of the latches and the rising and falling of the gate pulses. In these figures, reference codes L010-LOn0 denote the 0th-bit outputs of the D latches L31-L3n, reference codes LO17-LOn7 the 7th-bit outputs, and GPl-GPn gate pulses supplied to the selectors SEL1-SEL8.
As is evident from FIGS. 3 and 4, the transmission time delay of the signal LOn0 is longer than that of the signal L010 between the D latches L31-L3n and selectors SEL1-SEL8 since the signal line for the signal LOn0 is longer than that for the signal LO10, whereas the transmission time delay of the signal LO17 is longer than that of the signal LOn7 since the signal line for the signal LO17 is longer than that for the signal LOn7.
As is shown in FIG. 3, since there is a time period of 8 (n-1)/(n.times.f0) between the determination of the output LonO of the D latch L3n of the channel n and the generation of a gate pulse, the hatched signal to be multiplexed can be gated correctly, unless the transmission time delay is longer than the time period therebetween.
However, as is shown in FIG. 4, since the transmission time delay of the signal of the channel 1 is longer than that of the signal of the channel n in the case of the 7th-bit output, the determination point of the output LO17 of the D latch L31 of the channel 1 will be retarded from the generation of the gate pulse GP1 by a selector control section 32, and hence the hatched signal to be multiplexed will not be able to be gated, if its transmission time delay exceeds the width 8/(n.times.f0) of the gate pulse.
As described above, in the conventional time-division multiplexing apparatus, signal lines arranged between the D latches and n:1 selectors have different lengths, so that in the case of time-division multiplexing n-channel inputs to produce m-channel outputs, the transmission time delay of a signal transmitted through one of the signal lines inevitably differs from that of a signal transmitted through another line. In particular, if the transmission time delay exceeds m/(n.times.f0), correct multiplexing cannot be performed.